AI Infrastructure

An infrastructure architect must connect eight GPUs inside a single high-density training server so they share memory at maximum bandwidth without going through the CPU or PCIe bus. Which technology directly addresses this intra-node requirement?

• ANVLink and NVSwitch providing direct high-bandwidth GPU-to-GPU connectivitycheck_circle Correct
• BInfiniBand HDR host channel adapters installed in each GPU's PCIe slot
• CRoCE over a 400 GbE top-of-rack switch cabled back to each GPU server
• DA BlueField DPU offloading storage and network traffic from the host CPU

Why A is correct: NVLink is a dedicated point-to-point interconnect built into NVIDIA GPUs that bypasses PCIe, and NVSwitch aggregates multiple NVLink connections so every GPU in the node can communicate with every other GPU at full bandwidth simultaneously, enabling scale-up parallelism.

Why B is wrong: InfiniBand host channel adapters connect servers to an external switch fabric for inter-node communication; they traverse PCIe and do not provide the direct GPU-to-GPU low-latency path needed inside a single node.

Why C is wrong: RoCE over Ethernet is a valid inter-node fabric technology for scale-out clusters but introduces external switch hops and is not designed to replace the tight intra-node memory-bandwidth path that NVLink provides.

Why D is wrong: A DPU offloads networking, storage, and security processing from the CPU to free host resources, which is a valid data-centre optimisation, but it does not create direct GPU-to-GPU high-bandwidth connectivity within the node.

A data-centre architect is designing the network topology for a large GPU training cluster. Which fabric is specifically intended to carry GPU-to-GPU collective communications between compute nodes?

• AA dedicated InfiniBand compute fabric connecting all GPU nodes at high bandwidth and low latency.check_circle Correct
• BA 1 GbE out-of-band management network shared with the head nodes.
• CA high-throughput parallel filesystem network such as Lustre over Ethernet, which also carries checkpoint data.
• DThe provisioning and job-scheduling network used by the head nodes to distribute workloads to compute nodes.

Why A is correct: In a SuperPOD-style reference architecture, a dedicated InfiniBand compute fabric carries all inter-node GPU traffic including AllReduce and other collective operations. Its RDMA capabilities and low-latency switching are specifically matched to the demands of distributed training workloads.

Why B is wrong: Out-of-band management networks carry BMC and administrative traffic. They have far too little bandwidth and too high latency to serve collective training communications between GPUs.

Why C is wrong: Parallel filesystem networks are optimised for storage I/O throughput and are shared with checkpoint and dataset traffic. Running GPU collectives over the storage network would degrade both training and I/O performance.

Why D is wrong: Head nodes use a management or provisioning network for job dispatch and monitoring, not for the sustained high-bandwidth, low-latency traffic generated by GPU collective operations during training.

On a converged Ethernet fabric carrying both bulk storage traffic and latency-sensitive RDMA collective traffic, an engineer enables Priority Flow Control (PFC). What does PFC specifically do to keep the RDMA traffic class lossless?

• AIt pauses all traffic on the entire link whenever any single buffer begins to fill, regardless of the traffic priority
• BIt pauses traffic only on the specific priority class whose receive buffer is filling, while other classes continue flowingcheck_circle Correct
• CIt marks congested packets with a notification bit so that the sender reduces its transmission rate gradually over time
• DIt reorders the queued packets so that the highest priority class is always transmitted ahead of every lower class

Why A is wrong: It is tempting because this describes legacy IEEE 802.3x link-level pause, but that mechanism cannot distinguish traffic classes and would block latency-sensitive RDMA whenever bulk storage congests, which is exactly what PFC was designed to avoid.

Why B is correct: PFC operates per priority class using the 802.1p priority field, so it can issue a pause frame for only the congested class, preventing drops on the RDMA class while storage and other classes keep flowing, which is the behaviour a converged fabric needs.

Why C is wrong: It is tempting because this is a real congestion mechanism, but marking packets to signal a rate reduction is the role of Explicit Congestion Notification, not PFC, which acts by pausing rather than by marking packets.

Why D is wrong: It is tempting because priority queuing does favour higher classes, but that is scheduling rather than flow control; PFC prevents loss by pausing a class under buffer pressure, it does not reorder or schedule transmissions.

An infrastructure architect is explaining why a DPU can accelerate data-centre infrastructure services that a standard network interface card cannot. They point to the building blocks integrated onto the DPU itself. Which combination of components is characteristic of a data processing unit and accounts for this capability?

• AProgrammable Arm processor cores combined with a high-speed network adapter and dedicated hardware accelerators for tasks such as encryption and packet processing.check_circle Correct
• BA bank of tensor cores paired with high-bandwidth memory, optimised for matrix multiplication during model training.
• CA high-core-count x86 processor with large DDR capacity, intended to run the host operating system and the hypervisor.
• DA field-programmable gate array used purely as a reconfigurable network switch with no general-purpose processing cores of its own.

Why A is correct: Correct: a DPU integrates Arm cores for programmability, a network interface for connectivity, and purpose-built accelerators, which together let it run infrastructure services in hardware that a plain network card cannot.

Why B is wrong: Tempting because the DPU sits in AI servers alongside GPUs, but tensor cores and high-bandwidth memory describe a GPU; a DPU targets infrastructure offload, not training arithmetic.

Why C is wrong: Plausible because DPUs do run their own software, but the host operating system and hypervisor run on the server's x86 CPU; a DPU uses embedded Arm cores, not a high-core-count x86.

Why D is wrong: Tempting because DPUs perform packet processing in hardware, but a DPU is not a bare reconfigurable switch; it pairs accelerators with general-purpose programmable cores that run a full software stack.

During multi-node training, a profiler shows that incoming gradient tensors land in host system memory and are then copied across PCIe into GPU memory before the next compute step, and this staging copy adds latency on every step. The team wants the network adapter to write received data straight into GPU memory and skip the host bounce buffer. Which technology provides this direct path?

• AGPUDirect Storage, which moves data between local NVMe drives and GPU memory without staging through host memory
• BUnified Virtual Addressing, which gives host and device a single pointer space so an explicit copy is unnecessary
• CNVLink peer-to-peer access, which lets two GPUs in the same node read each other's memory without using PCIe
• DGPUDirect RDMA, which lets the network adapter DMA received data directly into GPU memory over PCIe, bypassing host memorycheck_circle Correct

Why A is wrong: GPUDirect Storage is a real direct path, but it targets the storage-to-GPU route over the local filesystem, not data arriving from the network adapter, so it does not address inter-node transfer staging.

Why B is wrong: Unified Virtual Addressing does present one address space, but it is a CUDA memory-management feature that simplifies pointers; it does not let the network adapter DMA into GPU memory, so the host staging copy still occurs.

Why C is wrong: NVLink peer-to-peer is correct for intra-node GPU-to-GPU access, but the bottleneck here is data arriving from a remote node via the network adapter, which NVLink does not handle.

Why D is correct: Correct: GPUDirect RDMA exposes GPU memory to the network adapter so received tensors are placed directly into GPU memory by RDMA, eliminating the host bounce-buffer copy and its added latency on every step.